Cita APA (7a ed.)

Pedre, S., Krajník, T., Todorovich, E., & Borensztejn, P. A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA.

Cita Chicago Style (17a ed.)

Pedre, S., T. Krajník, E. Todorovich, y P. Borensztejn. A Co-design Methodology for Processor-centric Embedded Systems with Hardware Acceleration Using FPGA.

Cita MLA (8a ed.)

Pedre, S., et al. A Co-design Methodology for Processor-centric Embedded Systems with Hardware Acceleration Using FPGA.