A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA

In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languages and tools. The whole system is designed using...

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Detalles Bibliográficos
Autores principales: Pedre, S., Krajník, T., Todorovich, E., Borensztejn, P.
Formato: CONF
Materias:
Abstraction level
Co-design flow
Co-design methodology
Code line
Design approaches
Design effort
Design method
Exact methods
Hardware acceleration
Hardware implementations
Hardware-accelerated
High-level modeling
Multiple robot
Profiling tools
Real-time image processing
Reference models
Software coding
Software domains
Software solution
Design
Embedded software
Embedded systems
Engineers
Image processing
Robot applications
Hardware
Acceso en línea:http://hdl.handle.net/20.500.12110/paper_97814673_v_n_p_Pedre
Aporte de:
Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA) de Universidad de Buenos Aires

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