Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
Packet processing is becoming much more challenging as networks evolve towards a multi-service platform. In particular, packet classification demands smaller processing times as data rates increase. To successfully meet this requirement, hardware-based classification architectures have become an are...
Guardado en:
| Autores principales: | Zerbini, Carlos A., Finochietto, Jorge M. |
|---|---|
| Formato: | conferenceObject |
| Lenguaje: | Inglés |
| Publicado: |
2022
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| Materias: | |
| Acceso en línea: | http://hdl.handle.net/11086/28727 |
| Aporte de: |
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