Reducing the LSQ and L1 data cache power consumption
In most modern processor designs, the HW dedicated to store data and instructions (memory hierarchy) has become a major consumer of power. In order to reduce this power consumption, we propose in this paper two techniques, one to filter accesses to the LSQ (Load-Store Queue) based on both timing and...
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| Autores principales: | , , , , , |
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| Formato: | Objeto de conferencia |
| Lenguaje: | Español |
| Publicado: |
2010
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| Materias: | |
| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/19346 |
| Aporte de: |
| Sumario: | In most modern processor designs, the HW dedicated to store data and instructions (memory hierarchy) has become a major consumer of power. In order to reduce this power consumption, we propose in this paper two techniques, one to filter accesses to the LSQ (Load-Store Queue) based on both timing and address information, and the other to filter accesses to the first level data cache based on a forwarding predictor.
Our simulation results show that the power consumption decreases in 30-40% in each structure, with a negligible performance penalty of less than 0.1%. |
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